Interrupt operations

An interrupt is a signal that makes the processor suspend its current program, run a special routine to service an event, and then return to where it left off. Interrupts let a processor respond quickly to external devices (keyboard, timer, ADC) without wasting time polling them. This topic covers types of interrupts, the interrupt service routine (ISR), and the step-by-step processing of interrupts, mainly using the 8085 and 8086 as examples.

Key concepts

• Polling vs interrupts: In polling, the CPU repeatedly checks each device's status, which wastes time. With interrupts, the device signals the CPU only when it needs service, giving better CPU utilisation and faster response.
• Classification of interrupts:
  • Hardware (external pins) vs software (instructions such as RST n in 8085 or INT n in 8086).
  • Maskable (can be disabled by software) vs non-maskable (cannot be disabled; used for critical events such as power failure).
  • Vectored (fixed ISR address) vs non-vectored (device supplies the address/instruction, e.g. INTR in 8085).
  • Edge-triggered vs level-triggered.
  • Internal exceptions (8086): divide error (type 0), single-step (type 1), overflow (type 4).
• 8085 hardware interrupts:

Interrupt	Priority	Vector address	Maskable	Trigger
TRAP	1 (highest)	0024H	No	edge and level
RST 7.5	2	003CH	Yes	rising edge
RST 6.5	3	0034H	Yes	level
RST 5.5	4	002CH	Yes	level
INTR	5 (lowest)	supplied by device	Yes	level, non-vectored

Vector address of RST n = $n\times8$ (in hex). E.g. RST 7.5 = 7.5×8 = 60 = 3CH.

• Software interrupts (8085): RST 0 to RST 7, vectoring to 0000H, 0008H, …, 0038H.
• Control instructions: EI (enable interrupts), DI (disable), SIM (set interrupt mask for RST 7.5, 6.5, 5.5 and serial output), RIM (read interrupt mask, pending interrupts and serial input). TRAP is not affected by EI/DI/SIM.
• 8086 interrupts: 256 interrupt types; the interrupt vector table occupies the first 1 KB of memory (00000H–003FFH), with 4 bytes (IP and CS) per type. The address of the vector for type n is $4n$. NMI is type 2; INTR is maskable using the IF flag (STI/CLI). The 8259 Programmable Interrupt Controller expands INTR into 8 prioritised interrupt lines and can be cascaded to 64.
• Interrupt Service Routine (ISR): The routine that services the device. Good practice: save registers (PUSH), keep it short, re-enable interrupts if nesting is allowed, restore registers (POP) and end with RET (8085) or IRET (8086).
• Interrupt processing sequence:
  1. Device asserts an interrupt request.
  2. CPU completes the current instruction.
  3. CPU checks whether the interrupt is enabled/unmasked and of sufficient priority.
  4. CPU acknowledges (e.g. INTA̅ for INTR) and disables further interrupts (in 8085, interrupts are disabled automatically).
  5. Return address (PC) is pushed onto the stack (8086 also pushes flags and CS).
  6. PC is loaded with the vector address; the ISR runs.
  7. ISR ends with return instruction; the saved PC is restored and the main program continues.
• Interrupt latency: Time from request to start of the ISR; reduced by short instructions and short critical sections.
• Priority and nesting: When several interrupts occur together, the highest priority is serviced first. A higher-priority interrupt can interrupt a lower-priority ISR if interrupts are re-enabled inside it.

High-yield points

• 8085 vectors: TRAP 0024H, RST 7.5 003CH, RST 6.5 0034H, RST 5.5 002CH.
• TRAP is non-maskable and highest priority; INTR is lowest and non-vectored.
• RST n vector $= 8n$ in hex (RST 7 → 0038H).
• 8086 IVT: first 1 KB (00000H–003FFH), 4 bytes per type, entry at $4n$.
• 8086 type 0 = divide error, type 2 = NMI.
• 8259 PIC: 8 interrupt lines, cascadable to 64.

Formulas

8085: $\text{Vector address of RST } n = (8n)_{10}$ converted to hex.

8086: $\text{IVT address for type } n = 4n$.

Worked example

Find the 8085 vector address for RST 6.5 and the 8086 IVT location for INT 21H.

1. RST 6.5: $6.5\times8 = 52_{10} = 34$H → 0034H.
2. INT 21H: type = 33 (decimal). $4\times33 = 132 = 84$H → IVT entry at 00084H–00087H.

Exam tips

• TRAP is the highest-priority, non-maskable interrupt of the 8085; INTR is the lowest and non-vectored.
• RST 7.5 is edge-triggered and has a latch, so a short pulse is remembered.
• SIM masks/unmasks RST 7.5, 6.5, 5.5 only.
• 8086 NMI = type 2; IVT occupies 1 KB at the bottom of memory.
• An ISR in 8086 ends with IRET (pops IP, CS and flags), not RET.

Exam-style questions

From Calmon's question bank, which has 25 questions on this topic.

1. What is meant by a vectored interrupt?

• A. The CPU must poll every device to find which one interrupted
• B. The CPU branches to an ISR address that is fixed or supplied for that interrupt source, without polling
• C. The interrupt can be disabled by a mask bit
• D. The interrupt is generated by a software instruction

Answer: B. For a vectored interrupt, the ISR address is predetermined (for example, TRAP goes to 0024H) or supplied by the source, so the CPU goes straight to the correct ISR.

2. Which 8085 instruction enables the maskable interrupts by setting the interrupt enable flip-flop?

• A. EI
• B. DI
• C. SIM
• D. RIM

Answer: A. EI sets the interrupt-enable flip-flop. DI clears it. SIM and RIM set and read the RST 7.5/6.5/5.5 masks.

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