Sequential logic circuit

Sequential circuits have memory: their outputs depend on present inputs and past history (the stored state). The basic memory element is the latch or flip-flop. This topic covers SR, gated, edge-triggered and master-slave flip-flops, registers built from flip-flops, uses of shift registers, and asynchronous and synchronous counters. Expect MOD-number, truth-table and "which flip-flop has race-around" questions.

Key concepts

• SR (RS) latch: Two cross-coupled NOR gates (active-high inputs) or NAND gates (active-low inputs). S=1 sets Q=1, R=1 resets Q=0, S=R=0 holds. For a NOR latch, S=R=1 is invalid (both outputs 0, and the next state is unpredictable when inputs are released).
• Gated (clocked) flip-flops: An enable/clock input allows the inputs to affect the output only when the clock is active. Gated SR, gated D (D latch).
• Flip-flop types and characteristic tables:

FF	Inputs	Characteristic equation	Notes
SR	S, R	$Q^+ = S + \bar RQ$ (SR=0)	S=R=1 forbidden
D	D	$Q^+ = D$	delay / data storage
JK	J, K	$Q^+ = J\bar Q + \bar KQ$	J=K=1 toggles
T	T	$Q^+ = T\oplus Q$	T=1 toggles; used in counters

• Level-triggered vs edge-triggered: A latch is level sensitive (transparent while enabled). An edge-triggered flip-flop samples inputs only at the rising (positive) or falling (negative) edge of the clock, achieved with a pulse-detecting circuit or master-slave arrangement. Setup time and hold time must be satisfied around the edge.
• Race-around condition: In a level-triggered JK flip-flop with J=K=1, the output toggles repeatedly while the clock is high if the clock pulse width exceeds the propagation delay. Cures: edge triggering, or the master-slave configuration.
• Master-slave flip-flop: Two flip-flops in series; the master is enabled when the clock is high, the slave when the clock is low (inverted clock). Output changes only once per clock cycle, eliminating race-around.
• Asynchronous inputs: Preset and Clear force the output regardless of the clock.
• Registers: Groups of flip-flops storing an n-bit word. Types by data movement:
  • SISO (serial-in serial-out), SIPO (serial-in parallel-out), PISO (parallel-in serial-out), PIPO (parallel-in parallel-out).
  • Bidirectional and universal shift registers (e.g. 74194) can shift left, right, load in parallel or hold.
• Applications of shift registers: serial ↔ parallel conversion (UARTs), time delay, multiplication/division by 2 (shift left/right), ring counter, Johnson (twisted ring) counter, sequence generators and pseudo-random (LFSR) generators.
• Ring counter: n flip-flops, one circulating 1, MOD-n. Johnson counter: inverted output fed back, MOD-2n.
• Asynchronous (ripple) counter: Only the first flip-flop gets the external clock; each later flip-flop is clocked by the previous output. Simple, but delays accumulate (total delay ≈ n × $t_{pd}$), causing glitches and limiting speed.
• Synchronous counter: All flip-flops share the same clock; logic gates decide which flip-flops toggle. Faster and glitch-free, but needs more logic. Designed using excitation tables.
• MOD-N counter: Counts N states. Needs $n$ flip-flops where $2^n \ge N$. A MOD-10 (decade) counter needs 4 flip-flops and is reset when the count reaches 1010. Up/down counters can count in both directions.

High-yield points

• JK: $Q^+ = J\bar Q + \bar KQ$; J = K = 1 toggles.
• NOR SR latch: S = R = 1 is invalid.
• Race-around occurs in level-triggered JK; cured by master-slave or edge triggering.
• Ring counter: MOD-n; Johnson counter: MOD-2n.
• MOD-N counter needs $\lceil\log_2N\rceil$ flip-flops.
• Ripple counter: $f_{max} \approx 1/(n\,t_{pd})$.

Formulas

$f_{out} = \frac{f_{clk}}{2^n}\ \text{(for an n-stage binary ripple counter's last stage)}$

$f_{max,\text{ripple}} \approx \frac{1}{n\,t_{pd}}$ $n$ = number of flip-flops, $t_{pd}$ = propagation delay of one flip-flop (s).

Number of flip-flops for MOD-N: $n = \lceil \log_2 N \rceil$.

Worked example

A 4-bit ripple counter uses flip-flops with $t_{pd} = 25$ ns, clocked at 1 MHz. What is the output frequency of the last stage and the maximum clock frequency?

1. Output of 4th stage: $1\ \text{MHz}/2^4 = 62.5$ kHz.
2. Total ripple delay: $4\times25 = 100$ ns.
3. $f_{max} \approx 1/100\ \text{ns} = 10$ MHz.

Check: a MOD-12 counter needs $\lceil\log_2 12\rceil = 4$ flip-flops.

Exam tips

• JK with J=K=1 toggles; this is how a T flip-flop is made from a JK.
• Race-around belongs to level-triggered JK; master-slave or edge-triggering removes it.
• D flip-flop has no invalid state — it is the basic register element.
• Ring counter: MOD-n; Johnson counter: MOD-2n with n flip-flops.
• A shift register shifting left by one place multiplies an unsigned number by 2.

Exam-style questions

From Calmon's question bank, which has 23 questions on this topic.

1. In a flip-flop logic symbol, what does a small triangle at the clock input together with a bubble (small circle) mean?

• A. Level triggered, active HIGH
• B. Negative-edge triggered
• C. Asynchronous clear input
• D. Positive-edge triggered

Answer: B. The triangle (dynamic indicator) marks edge triggering, and the bubble marks inversion. Together they mean the flip-flop is triggered on the falling (negative) edge.

2. A MOD-6 asynchronous up-counter is made from a 3-bit ripple counter ($Q_2Q_1Q_0$, with $Q_2$ as the MSB) and flip-flops with active-LOW clear inputs. A NAND gate clears all flip-flops as soon as the count 110 appears. Which outputs must feed the NAND gate?

• A. $Q_2$ and $Q_0$
• B. $Q_1$ and $Q_0$
• C. $Q_2$ and $Q_1$
• D. $Q_2$, $Q_1$ and $Q_0$

Answer: C. $6 = 110_2$, so $Q_2$ and $Q_1$ are both 1 for the first time at the count of 6 (counts 0–5 never have both HIGH). NAND-ing $Q_2$ and $Q_1$ gives a LOW that clears the counter, so it counts 0–5.

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