Semiconductor devices

Semiconductor devices are the building blocks of all modern electronics. This topic covers the p-n junction diode and its V-I characteristic, the bipolar junction transistor (BJT) with its three configurations and biasing methods, the small-signal and large-signal models used for analysis, and the MOSFET together with CMOS logic, which is the basis of almost every digital IC today. MCQs typically test characteristic values, the comparison of configurations, and the working principle of devices.

Key concepts

• Intrinsic and extrinsic semiconductors: Pure Si or Ge is intrinsic. Adding a pentavalent impurity (P, As, Sb) gives n-type (electrons majority); a trivalent impurity (B, Al, Ga, In) gives p-type (holes majority).
• P-N junction: Diffusion of carriers across the junction forms a depletion region with a barrier potential of about 0.7 V for Si and 0.3 V for Ge.
• Diode characteristics: In forward bias, current is negligible until the cut-in (knee) voltage, then rises exponentially. In reverse bias, only a tiny reverse saturation current $I_s$ flows (nA for Si, µA for Ge) until breakdown.
• Breakdown: Zener breakdown (heavily doped, below about 5 V, field emission) and avalanche breakdown (lightly doped, higher voltage, impact ionisation). Zener diodes are used as voltage regulators.
• Diode applications: rectifiers (half-wave, full-wave, bridge), clippers, clampers, voltage multipliers; special diodes include LED, photodiode, varactor and Schottky.
• BJT: Three-layer device (npn or pnp) with emitter (heavily doped), base (thin, lightly doped) and collector (moderately doped, largest). $I_E = I_B + I_C$, $\alpha = I_C/I_E$ (≈0.95–0.99), $\beta = I_C/I_B$ (typically 50–300), $\beta = \alpha/(1-\alpha)$.
• Regions of operation: Active (BE forward, CB reverse) — amplifier; Saturation (both forward) — switch ON; Cut-off (both reverse) — switch OFF.

Configuration	Current gain	Voltage gain	Input Z	Output Z	Phase shift	Use
Common Base	α < 1	High	Very low	Very high	0°	High-frequency
Common Emitter	β (high)	High	Medium	Medium	180°	General amplifier
Common Collector	β+1 (high)	≈1	High	Low	0°	Buffer (emitter follower)

• Biasing: Sets the Q-point in the active region and keeps it stable against changes in temperature and β. Methods: fixed bias (poor stability), collector-to-base feedback, and voltage-divider bias (best stability, most used). Stability factor $S = dI_C/dI_{CO}$; lower S is better. Thermal runaway is avoided with good biasing and an emitter resistor.
• Large-signal model: Used for DC/bias analysis and switching — $V_{BE} \approx 0.7$ V, $I_C = \beta I_B$ in active region, $V_{CE(sat)} \approx 0.2$ V.
• Small-signal model: Linearised model around the Q-point for AC analysis. The hybrid-π model uses $r_\pi = \beta/g_m$, transconductance $g_m = I_C/V_T$ (thermal voltage $V_T = kT/q \approx 26$ mV at 300 K), and output resistance $r_o$. The h-parameter model uses $h_{ie}, h_{fe}, h_{re}, h_{oe}$, where $h_{fe} \approx \beta$.
• MOSFET: A voltage-controlled device (gate insulated by SiO₂, so input impedance is extremely high). In an enhancement n-MOSFET, no channel exists at $V_{GS}=0$; when $V_{GS}$ exceeds the threshold voltage $V_{th}$, an inversion layer forms an n-channel. A depletion MOSFET has a built-in channel and conducts at $V_{GS}=0$. Regions: cut-off, linear (triode), saturation. Saturation current (for $V_{DS} \ge V_{GS}-V_{th}$): $I_D = k(V_{GS}-V_{th})^2$, with $k = \tfrac12\mu_nC_{ox}W/L$.
• CMOS: Complementary pairs of nMOS and pMOS. In a CMOS inverter, the pMOS pulls the output high and the nMOS pulls it low; only one conducts in steady state, so static power is nearly zero. Advantages: very low power, high noise margin, high packing density. Used in microprocessors, memories and image sensors.

High-yield points

• Barrier potential: Si ≈ 0.7 V, Ge ≈ 0.3 V.
• $I_E = I_B + I_C$ and $\beta = \alpha/(1-\alpha)$.
• CE: 180° phase shift; CC: voltage gain ≈ 1 (buffer); CB: lowest input impedance.
• Voltage-divider bias gives the best Q-point stability.
• Enhancement MOSFET conducts only when $V_{GS} > V_{th}$; depletion MOSFET conducts at $V_{GS} = 0$.
• CMOS static power ≈ 0; dynamic power $\propto CV^2f$.

Formulas

$I_D = I_s\left(e^{V_D/(\eta V_T)} - 1\right)$ $I_s$ = reverse saturation current (A), $V_D$ = diode voltage (V), $\eta$ = ideality factor (1–2), $V_T = kT/q \approx 26$ mV at 300 K.

$\beta = \frac{\alpha}{1-\alpha}, \qquad \alpha = \frac{\beta}{1+\beta}$

$g_m = \frac{I_C}{V_T}, \qquad r_\pi = \frac{\beta}{g_m}$

Worked example

A BJT has $\alpha = 0.98$ and $I_B = 40\ \mu$A. Find β, $I_C$ and $I_E$.

1. $\beta = 0.98/(1-0.98) = 0.98/0.02 = 49$.
2. $I_C = \beta I_B = 49\times40\ \mu A = 1.96$ mA.
3. $I_E = I_C + I_B = 1.96 + 0.04 = 2.00$ mA. Check: $\alpha = 1.96/2.00 = 0.98$ ✓.

Exam tips

• Emitter is the most heavily doped; base is the thinnest and lightest doped; collector is the largest (to dissipate heat).
• CE gives 180° phase shift; CC (emitter follower) has voltage gain ≈ 1 and is used for impedance matching.
• BJT is current-controlled and bipolar; FET/MOSFET is voltage-controlled and unipolar.
• Reverse saturation current roughly doubles for every 10 °C rise.
• CMOS consumes power mainly while switching (dynamic power $\propto CV^2f$), not in steady state.

Exam-style questions

From Calmon's question bank, which has 25 questions on this topic.

1. A silicon diode has a reverse saturation current of 10 nA at 25 °C. Assuming it doubles for every 10 °C rise, its value at 45 °C is:

• A. 30 nA
• B. 40 nA
• C. 80 nA
• D. 20 nA

Answer: B. A 20 °C rise is two doublings: $10 \times 2^2 = 40$ nA.

2. A BJT has a current gain $\beta = 100$. Its common-base current gain $\alpha$ is:

• A. 0.999
• B. 1.010
• C. 0.990
• D. 0.909

Answer: C. $\alpha = \dfrac{\beta}{1+\beta} = \dfrac{100}{101} \approx 0.990$.

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