Combinational and arithmetic circuits

Combinational circuits produce outputs that depend only on present inputs; they have no memory. This topic covers data-routing circuits (multiplexers, demultiplexers), code converters (decoders, encoders) and arithmetic circuits (adders, subtractors), together with how computers represent and operate on unsigned and signed binary numbers. Many MCQs ask for the number of select lines, output of a given circuit, or the 2's complement of a number.

Key concepts

• Multiplexer (MUX): "Many to one" data selector. It has $2^n$ data inputs, $n$ select lines and one output. A 4:1 MUX: $Y=\bar S_1\bar S_0 I_0+\bar S_1S_0I_1+S_1\bar S_0I_2+S_1S_0I_3$. A $2^n$:1 MUX can implement any Boolean function of $n$ variables (or $n+1$ variables if one variable is fed to the data inputs). Used in data selection, parallel-to-serial conversion and as universal logic.
• Demultiplexer (DEMUX): "One to many" — routes one input to one of $2^n$ outputs chosen by $n$ select lines. Used for serial-to-parallel conversion and distributing data.
• Decoder: Converts an n-bit binary code into one of $2^n$ active outputs (n-to-$2^n$ line decoder). Each output corresponds to a minterm, so a decoder plus OR gates can implement any function. A decoder with an enable input acts as a DEMUX. Examples: 3-to-8 (74138), BCD-to-7-segment decoder for displays. Used for memory address decoding.
• Encoder: The reverse — $2^n$ inputs to an n-bit code (e.g. 8-to-3 octal-to-binary, decimal-to-BCD 10-to-4). A simple encoder fails if two inputs are active; a priority encoder outputs the code of the highest-priority active input (e.g. 74148), and a "valid" output tells whether any input is active.
• Half adder: Adds two bits. Sum $S=A\oplus B$, Carry $C=AB$.
• Full adder: Adds A, B and carry-in. $S=A\oplus B\oplus C_{in}$, $C_{out}=AB+C_{in}(A\oplus B)$. Built from two half adders and an OR gate.
• Ripple-carry adder: n full adders chained; slow because carry propagates through every stage. A carry look-ahead adder computes carries in parallel using generate $G=AB$ and propagate $P=A\oplus B$.
• Half subtractor: Difference $D=A\oplus B$, Borrow $B_o=\bar AB$. Full subtractor: $D=A\oplus B\oplus B_{in}$, $B_{out}=\bar AB+\overline{(A\oplus B)}B_{in}$.
• Binary subtraction with complements: Adding the 2's complement of B to A gives $A-B$. One adder plus XOR gates (controlled by a mode bit M) forms an adder/subtractor: M=0 adds, M=1 inverts B and sets carry-in to 1.
• Unsigned numbers: n bits represent 0 to $2^n-1$. A carry out of the MSB means overflow.
• Signed number representations (n bits):

Method	Range	Notes
Sign-magnitude	$-(2^{n-1}-1)$ to $+(2^{n-1}-1)$	two zeros (+0, −0)
1's complement	$-(2^{n-1}-1)$ to $+(2^{n-1}-1)$	two zeros; end-around carry
2's complement	$-2^{n-1}$ to $+(2^{n-1}-1)$	one zero; used in all modern CPUs

An 8-bit 2's-complement number ranges from −128 to +127.

• Overflow in signed addition: Occurs when adding two numbers of the same sign gives a result of the opposite sign. Detected as $V = C_{n}\oplus C_{n-1}$ (carry into MSB XOR carry out of MSB).
• BCD addition: If a 4-bit sum exceeds 9 or produces a carry, add 6 (0110) to correct it.

High-yield points

• A $2^n$:1 MUX has $n$ select lines; 16:1 needs 4.
• Half adder: $S = A\oplus B$, $C = AB$; full adder $C_{out} = AB + C_{in}(A\oplus B)$.
• n-bit 2's complement range: $-2^{n-1}$ to $2^{n-1}-1$ (8-bit: −128 to +127).
• Signed overflow: $V = C_n \oplus C_{n-1}$.
• BCD addition: add 0110 when the sum exceeds 9 or produces a carry.
• A decoder with an enable input works as a DEMUX.

Formulas

$\text{2's complement of } N = 2^n - N$

Number of select lines for an $m$:1 MUX: $n = \log_2 m$.

$C_{i+1} = G_i + P_iC_i, \quad G_i = A_iB_i,\ P_i = A_i\oplus B_i$

Worked example

Compute $5 - 7$ in 4-bit 2's complement.

1. $5 = 0101$, $7 = 0111$.
2. 2's complement of 7: invert → 1000, add 1 → 1001.
3. $0101 + 1001 = 1110$ (no carry out).
4. MSB = 1, so the result is negative: 2's complement of 1110 = 0001+1 = 0010 = 2. Result = −2 ✓.

MUX check: a 16:1 MUX needs $\log_2 16 = 4$ select lines.

Exam tips

• MUX = data selector; DEMUX = data distributor; decoder with enable = DEMUX.
• Number of select lines is set by the number of inputs (MUX) or outputs (DEMUX), not by data width.
• 2's complement has only one zero and one more negative number than positive.
• Half adder has 2 inputs; full adder has 3 inputs and 2 outputs.
• Overflow can only happen when operands have the same sign.

Exam-style questions

From Calmon's question bank, which has 24 questions on this topic.

1. The 8-bit two's complement numbers 01100100 and 00111100 are added. What is the 8-bit result, and does signed overflow occur?

• A. 10100000; no overflow
• B. 10100000; overflow occurs (the result reads as $-96$)
• C. 01100000; overflow occurs
• D. 00100000; no overflow

Answer: B. $100 + 60 = 160 = 10100000_2$. Adding two positive numbers gave a result with sign bit 1 (which reads as $-96$), so overflow has occurred because $160 > 127$.

2. An 8-to-3 priority encoder gives D7 the highest priority and D0 the lowest. If only inputs D5 and D2 are HIGH, the binary output is:

• A. 010
• B. 011
• C. 101
• D. 111

Answer: C. A priority encoder outputs the code of the highest-priority active input. D5 outranks D2, so the output is $5 = 101_2$.

Practise AExE02 questions →