Logic families and ICs

Digital ICs are grouped into "logic families" according to the circuit technology used to build their gates. Each family — RTL, DTL, TTL, ECL, CMOS — offers a different balance of speed, power, noise immunity and fan-out. Understanding these trade-offs explains why TTL dominated in the 1970s–80s and why CMOS dominates today. NEC MCQs typically ask for the definitions of fan-out, noise margin and propagation delay, typical values for TTL and CMOS, and which family is fastest or uses the least power.

Key concepts

Evolution of logic families

1. RTL (Resistor-Transistor Logic) — early 1960s, first IC family.
2. DTL (Diode-Transistor Logic) — improved fan-out.
3. TTL (Transistor-Transistor Logic) — 1960s–80s standard (74xx series), many sub-families (74S, 74LS, 74ALS, 74F).
4. ECL (Emitter-Coupled Logic) — fastest bipolar, non-saturating.
5. MOS → CMOS (4000 series, 74HC/HCT) — dominant today because of low power and high density.
6. BiCMOS combines bipolar output drive with CMOS logic.

Classification

• Bipolar families: saturated (RTL, DTL, TTL, I²L) and non-saturated (Schottky TTL, ECL).
• Unipolar (MOS) families: PMOS, NMOS, CMOS.

Characteristics (figures of merit)

• Propagation delay ($t_p$): average of $t_{PHL}$ and $t_{PLH}$; time from input change to output change. Lower = faster.
• Power dissipation: average power per gate.
• Speed-power product (figure of merit): $t_p \times P$ in pJ; lower is better.
• Fan-out: number of gate inputs of the same family that one output can drive reliably. Fan-in: number of inputs a gate has.
• Noise margin: $NM_H = V_{OH(min)} - V_{IH(min)}$, $NM_L = V_{IL(max)} - V_{OL(max)}$.
• Logic levels, supply voltage, operating temperature, cost.

Typical comparison

Family	$t_p$ (ns)	Power/gate	Fan-out	Noise immunity
RTL	~12	~12 mW	~5	poor
DTL	~30	~8–12 mW	~8	good
Standard TTL (74)	~10	~10 mW	10	0.4 V
LS-TTL	~9.5	~2 mW	20	0.3 V (low), 0.7 V (high)
ECL	~1 or less	~25–40 mW	~25	poor (~0.2 V)
CMOS	depends on supply (≈ tens of ns for 4000, few ns for HC)	nW static	> 50	high (a large fraction of $V_{DD}$)

Simple gate circuits

• RTL NOR gate: each input drives the base of a transistor through a resistor; collectors are tied together to a common collector resistor. Any input HIGH saturates its transistor and pulls the output LOW → NOR. Drawbacks: low fan-out, poor noise margin, high power.
• DTL NAND gate: input diodes form an AND function at a node; that node drives a transistor inverter through level-shifting diodes. If any input is LOW, its diode conducts, the node is low, the transistor is off, output HIGH. All inputs HIGH → transistor saturates → output LOW → NAND. Slow because of saturation and charge storage.
• TTL NAND gate (7400): input stage is a multi-emitter transistor (replaces DTL's diodes); next a phase-splitter transistor; output is a totem-pole pair (active pull-up and pull-down) giving low output impedance and fast switching in both directions. An unconnected TTL input floats HIGH.

TTL output variants

• Totem-pole: fast, but outputs must not be tied together.
• Open-collector: requires external pull-up resistor; outputs can be wired-AND; used for driving LEDs, relays, buses.
• Tri-state: HIGH, LOW, or high-impedance (enabled by control line) — used for bus systems.

TTL voltage levels (5 V supply): $V_{IL(max)} = 0.8$ V, $V_{IH(min)} = 2.0$ V, $V_{OL(max)} = 0.4$ V, $V_{OH(min)} = 2.4$ V.

High-yield points

• TTL levels: $V_{IL(max)} = 0.8$ V, $V_{IH(min)} = 2.0$ V, $V_{OL(max)} = 0.4$ V, $V_{OH(min)} = 2.4$ V, so both noise margins are 0.4 V.
• Standard TTL: fan-out 10, $t_p \approx 10$ ns, about 10 mW per gate.
• ECL is fastest (non-saturating); CMOS has the lowest static power.
• Basic gates: RTL NOR, DTL NAND, TTL NAND.
• Totem-pole outputs must not be wired together; open-collector outputs can be (wired-AND).

Formulas

$NM_H = V_{OH(min)} - V_{IH(min)},\qquad NM_L = V_{IL(max)} - V_{OL(max)}$

$t_p = \frac{t_{PHL} + t_{PLH}}{2},\qquad \text{SPP} = t_p \times P_D\ \text{(joule)}$

$\text{Fan-out} = \min\left(\frac{I_{OL(max)}}{I_{IL(max)}},\ \frac{I_{OH(max)}}{I_{IH(max)}}\right)$

Worked example

Standard TTL: $I_{OL} = 16$ mA, $I_{IL} = 1.6$ mA, $I_{OH} = 400$ μA, $I_{IH} = 40$ μA. Find fan-out and noise margins.

1. LOW-state fan-out = 16/1.6 = 10.
2. HIGH-state fan-out = 400/40 = 10.
3. Fan-out = 10.
4. $NM_H = 2.4 - 2.0 = 0.4$ V; $NM_L = 0.8 - 0.4 = 0.4$ V.

Exam tips

• ECL is the fastest (non-saturating); CMOS has the lowest static power.
• TTL basic gate is NAND; RTL basic gate is NOR.
• Multi-emitter input transistor and totem-pole output are signatures of TTL.
• A floating TTL input behaves as logic 1.
• Speed-power product is the standard figure of merit; lower is better.

Exam-style questions

From Calmon's question bank, which has 25 questions on this topic.

1. How do 54-series TTL ICs differ from the corresponding 74-series ICs?

• A. They use CMOS technology
• B. They are a faster Schottky version
• C. They have open-collector outputs only
• D. They are rated for the wider military temperature range (−55 °C to +125 °C)

Answer: D. The 54 series is the military-grade version (−55 °C to +125 °C); the 74 series is for the commercial range (0 °C to 70 °C).

2. The fan-out of a logic gate is:

• A. The time it takes the output to change state
• B. The number of inputs the gate has
• C. The maximum number of similar gate inputs its output can drive while staying within specified logic levels
• D. The power it draws from the supply

Answer: C. Fan-out is the number of standard loads one output can drive reliably; the number of inputs is the fan-in.

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