JFET and MOSFET

Field-effect transistors (FETs) control current with an electric field rather than an input current, so they draw almost no gate current and offer very high input impedance. The JFET was the first practical FET; the MOSFET is now the dominant device in the world, forming billions of switches in every processor through CMOS technology, and also serving as power switches in inverters and chargers. This topic covers JFET construction and characteristics, MOSFET types and their I-V equations, MOSFET as amplifier and switch, biasing, and CMOS.

Key concepts

FET basics

• Unipolar device (one carrier type), voltage-controlled, high input impedance ($10^9$–$10^{14}$ Ω), less noisy, better thermal stability than BJT (no thermal runaway), but usually lower gain-bandwidth.
• Terminals: source (S), drain (D), gate (G), sometimes body/substrate (B).

JFET

• Construction: an n-type (or p-type) channel with heavily doped p⁺ gate regions on the sides.
• Operation: gate-source junction is always reverse biased. Increasing $|V_{GS}|$ widens the depletion regions and narrows the channel.
• Pinch-off voltage $V_P$: $V_{DS}$ at which the channel pinches off and current saturates (for $V_{GS}=0$). Cut-off $V_{GS(off)}$: gate voltage at which $I_D = 0$; numerically $|V_{GS(off)}| = |V_P|$.
• $I_{DSS}$: maximum drain current, at $V_{GS} = 0$.
• Regions: ohmic (voltage-controlled resistor), saturation (constant current, amplifier), cut-off, breakdown.
• JFET is a depletion-mode-only device.

MOSFET structure: metal (or polysilicon) gate isolated from the channel by a thin SiO₂ layer — therefore even higher input impedance and gate can be either polarity in depletion type.

Types of MOSFET

Type	Channel at $V_{GS}=0$	Turned on by
n-channel enhancement	none	$V_{GS} > V_T$ (positive)
p-channel enhancement	none	$V_{GS} < V_T$ (negative)
n-channel depletion	exists	can operate with $V_{GS}$ negative (depletion) or positive (enhancement)
p-channel depletion	exists	opposite polarities

Enhancement MOSFET symbol shows a broken channel line; depletion shows a solid line.

I-V characteristics (n-channel enhancement)

• Cut-off: $V_{GS} < V_T$, $I_D = 0$.
• Triode/linear: $V_{DS} < V_{GS} - V_T$, $I_D = k_n[(V_{GS}-V_T)V_{DS} - V_{DS}^2/2]$.
• Saturation: $V_{DS} \ge V_{GS} - V_T$, $I_D = \frac{k_n}{2}(V_{GS}-V_T)^2$ (square law), where $k_n = \mu_nC_{ox}W/L$.
• Channel-length modulation adds a factor $(1 + \lambda V_{DS})$.

MOSFET as amplifier: biased in saturation; transconductance $g_m = k_n(V_{GS}-V_T) = 2I_D/(V_{GS}-V_T)$. Common-source voltage gain $A_v \approx -g_mR_D$ (180° phase shift). Common-drain = source follower (gain ≈ 1); common-gate = low input impedance.

MOSFET as switch: OFF in cut-off, ON in triode with small $R_{DS(on)}$. Power MOSFETs switch fast, are voltage driven and are used in SMPS, motor drives, solar inverters.

Biasing: fixed bias, self bias (source resistor, used for JFET/depletion), voltage-divider bias (common for enhancement MOSFET), drain-feedback bias. Goal: stable Q-point in saturation.

CMOS

• Complementary pair: a PMOS (pull-up) and an NMOS (pull-down) with common gates and drains form an inverter.
• Input high → NMOS on, PMOS off → output low; input low → output high.
• In either steady state one transistor is off, so static power is nearly zero; power is consumed mainly during switching ($P = CV_{DD}^2f$).
• Advantages: very low power, high noise margin, high fan-out, high packing density. Disadvantage: sensitive to static discharge.

Applications: MOSFET/CMOS in microprocessors, memories (DRAM, flash), image sensors, analog switches, op-amp input stages, power electronics; JFET in low-noise preamplifiers, analog switches, constant-current sources.

High-yield points

• JFET (Shockley): $I_D = I_{DSS}(1 - V_{GS}/V_P)^2$; $I_{DSS}$ flows at $V_{GS} = 0$.
• Enhancement MOSFET has no channel at $V_{GS} = 0$; an n-channel device conducts when $V_{GS} > V_T$.
• MOSFET saturation: $I_D = \frac{k_n}{2}(V_{GS} - V_T)^2$ (square law).
• CMOS static power ≈ 0; dynamic power $P = CV_{DD}^2f$.
• FET: unipolar, voltage-controlled, very high input impedance; BJT: bipolar, current-controlled.

Formulas

JFET (Shockley's equation): $I_D = I_{DSS}\left(1 - \frac{V_{GS}}{V_P}\right)^2$ $g_m = g_{m0}\left(1 - \frac{V_{GS}}{V_P}\right),\quad g_{m0} = \frac{2I_{DSS}}{|V_P|}$

where $I_D$ in A, voltages in V, $g_m$ in siemens.

Worked example

A JFET has $I_{DSS} = 10$ mA and $V_P = -4$ V. Find $I_D$ and $g_m$ at $V_{GS} = -2$ V.

1. $1 - V_{GS}/V_P = 1 - (-2)/(-4) = 1 - 0.5 = 0.5$.
2. $I_D = 10 \times 0.5^2 = 2.5$ mA.
3. $g_{m0} = 2\times10/4 = 5$ mS; $g_m = 5 \times 0.5 = 2.5$ mS.

Exam tips

• JFET gate is always reverse biased; MOSFET gate is insulated — both draw negligible gate current.
• Enhancement MOSFET has no channel at $V_{GS} = 0$; depletion MOSFET and JFET do.
• FET saturation region = amplifier region (unlike BJT where "saturation" means switch ON).
• CMOS static power dissipation ≈ 0; dynamic power ∝ $fCV^2$.
• FET is unipolar, voltage-controlled; BJT is bipolar, current-controlled.

Exam-style questions

From Calmon's question bank, which has 25 questions on this topic.

1. For an n-channel JFET, what is the drain current when $V_{GS} = V_P$ (the gate-source cut-off voltage)?

• A. $2I_{DSS}$
• B. Approximately zero
• C. $I_{DSS}$
• D. $I_{DSS}/2$

Answer: B. From $I_D = I_{DSS}(1 - V_{GS}/V_P)^2$, $I_D = 0$ when $V_{GS} = V_P$: the depletion regions close the channel completely.

2. For a very small $V_{DS}$ (deep in the ohmic/triode region), a MOSFET behaves as:

• A. A resistor whose value is controlled by $V_{GS}$
• B. An open circuit
• C. A constant-current source
• D. A forward-biased diode

Answer: A. For small $V_{DS}$, $I_D$ is nearly proportional to $V_{DS}$ with a slope set by $(V_{GS} - V_T)$, so the channel acts as a voltage-controlled resistor.

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