Microprocessor system

A microprocessor on its own cannot do useful work; it needs memory to hold programs and data, and I/O devices to communicate with the outside world. This topic covers memory types and the memory hierarchy, interfacing memory and I/O to the processor, parallel interfacing using the 8255 Programmable Peripheral Interface, serial communication (synchronous and asynchronous, RS-232 and similar standards), and Direct Memory Access with the 8237/8257 DMA controller.

Key concepts

• Memory classification:
  • RAM (volatile): SRAM uses flip-flops (fast, no refresh, costly; used for cache). DRAM stores charge on a capacitor (dense, cheap, needs periodic refresh; used for main memory).
  • ROM (non-volatile): Mask ROM (factory programmed), PROM (one-time programmable), EPROM (erased by UV light), EEPROM (electrically erased byte by byte), Flash (electrically erased in blocks; used in USB drives and SSDs).
  • Secondary storage: magnetic disk, optical disk, SSD.
• Memory hierarchy: Registers → cache → main memory → secondary storage. Moving down: capacity increases, cost per bit falls, access time increases. The hierarchy works because of locality of reference (temporal and spatial).
• Memory interfacing: The processor's address lines are split: lower lines go directly to the memory chip's address pins; higher lines are decoded (using gates or a decoder such as the 74138) to generate chip select. Control signals RD̅, WR̅ and IO/M̅ select read/write and memory vs I/O. Absolute (full) decoding uses all address lines (unique addresses); partial decoding ignores some lines (cheaper but creates foldback/mirror addresses).
• I/O interfacing:
  • I/O-mapped I/O (isolated I/O): separate 8-bit port address space (256 ports in the 8085), accessed only with IN/OUT instructions; IO/M̅ = 1.
  • Memory-mapped I/O: devices occupy memory addresses; all memory instructions can be used, but memory space is reduced.
• 8255 PPI (Programmable Peripheral Interface): A parallel I/O chip with three 8-bit ports A, B and C (port C can be split into two 4-bit halves) and a control register, selected by A1, A0. Modes:
  • BSR (bit set/reset) mode: sets or clears individual bits of port C.
  • Mode 0: simple I/O.
  • Mode 1: strobed (handshake) I/O, using port C lines for handshaking.
  • Mode 2: bidirectional bus (port A only). The control word's bit D7 = 1 selects I/O mode; D7 = 0 selects BSR mode.
• Serial interface: Sends data one bit at a time over fewer wires, suitable for long distances. Chips: 8251 USART. Terms: baud rate (signal changes per second), bit rate; simplex, half-duplex and full-duplex links.
• Synchronous vs asynchronous transmission:

Feature	Asynchronous	Synchronous
Clock	not sent; each side has its own	shared or recovered clock
Framing	start bit + data + optional parity + stop bit(s) per character	blocks of data with sync characters
Overhead	high (e.g. 2–3 bits per byte)	low
Speed	lower	higher
Example	UART, keyboard	SPI, HDLC

• Serial interface standards: RS-232 (single-ended, logic 1 = −3 to −15 V, logic 0 = +3 to +15 V, about 15 m at low speed, DB-9/DB-25 connectors; DTE/DCE terminology). RS-422 (differential, longer distance), RS-485 (differential, multi-drop, up to ~1200 m), USB, I²C and SPI for short on-board links. MAX232 converts TTL to RS-232 levels.
• Direct Memory Access (DMA): Lets a peripheral transfer blocks of data directly to/from memory without the CPU executing instructions for each byte. The DMA controller (8257 or 8237) requests the bus with HOLD; the CPU finishes the current machine cycle, floats its buses and replies with HLDA; the controller then generates addresses and control signals. Transfer modes: burst (block), cycle stealing, and transparent. Used for disk, sound and network transfers.

High-yield points

• SRAM: flip-flops, no refresh, cache. DRAM: capacitor, needs refresh, main memory.
• 8255: 3 ports, 24 I/O lines; D7 = 1 I/O mode, D7 = 0 BSR mode; Mode 2 only on port A.
• I/O-mapped I/O in 8085: 256 ports, IN/OUT only, IO/M̅ = 1.
• RS-232: logic 1 (mark) = −3 to −15 V.
• DMA: controller asserts HOLD; CPU replies HLDA and floats its buses.
• Async 8N1 frame = 10 bits, so 9600 baud gives 960 characters/s.

Formulas

$\text{Memory size} = 2^{n} \times m \text{ bits}$ $n$ = number of address lines, $m$ = data width (bits).

$\text{Data rate (async)} = \frac{\text{baud}}{\text{bits per frame}}\ \text{characters/s}$

Worked example

Characters are sent asynchronously at 9600 baud with 1 start bit, 8 data bits, no parity and 1 stop bit. How many characters per second, and what fraction is overhead?

1. Bits per frame = 1 + 8 + 1 = 10.
2. Characters/s = 9600/10 = 960.
3. Overhead = 2/10 = 20%.

Memory check: a chip with 12 address lines and 8 data lines stores $2^{12}\times8$ bits = 4 KB.

Exam tips

• SRAM: fast, no refresh, cache. DRAM: refresh needed, main memory.
• EPROM is erased by UV light; EEPROM electrically.
• 8255 has 3 ports, 24 I/O lines; only port A supports Mode 2.
• In DMA, the CPU gives up the bus in response to HOLD by asserting HLDA.
• RS-232 uses negative voltage for logic 1 (mark).

Exam-style questions

From Calmon's question bank, which has 24 questions on this topic.

1. An asynchronous serial link runs at 9600 bps. Each character is sent with 1 start bit, 8 data bits, no parity and 1 stop bit. What is the maximum number of characters transferred per second?

• A. 9600
• B. 1067
• C. 1200
• D. 960

Answer: D. Each character takes $1 + 8 + 1 = 10$ bits, so the rate is $9600/10 = 960$ characters per second.

2. How many programmable I/O lines does the 8255 PPI provide?

• A. 24
• B. 8
• C. 32
• D. 16

Answer: A. The 8255 has three 8-bit ports (A, B and C), giving $3 \times 8 = 24$ I/O lines.

Practise AExE02 questions →